Design Verification Lead / Engineer

This role will oversee architecture of a verification environment from scratch. The role involves creating test plans and implementing a top-down DV flow in collaboration with the design and architecture teams, implementing robust and re-usable DV environments for deployment across various classes of devices. Responsibilities: 1. Responsible for architecting DV methodology, flow development, test plan creation and execution 2. Perform chip verification in cooperation with design, architecture, …