Senior Design Verification Engineer

Role - Design Verification Engineer Experience - 5years Location - Bangalore JD Design Verification • Understanding the business requirements and functional specifications of the IPs, subsystems and SOC • Creating Verification Environment Architecture document • Reviewing and Revising: working towards meeting agreed upon acceptance criteria • Developing code in System Verilog, UVM (Universal Verification Methodology), C for Unit, Subsystem and SOC level verification • Performing RTL simulations…