Field-Programmable Gate Arrays Engineer

RTL FPGA Design Engineers Experience : 1-3 years Location : Hyderabad Expertise RTL Coding in Verilog, System Verilog or VHDL · Strong understanding of FPGA flow, Logic design, Digital design etc. · Knowledge in Xilinx FPGA architecture · Good Knowledge in Tcl, Python scripting. Interested,please share your updated resume to janagaradha.n@acldigital.com